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Abstract

A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.

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