Data processing system simultaneously performing plural translations of virtual addresses having different page sizes
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United States of America Patent
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Jul 4, 1995
Grant Date -
N/A
app pub date -
Dec 14, 1992
filing date -
Dec 12, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processing system which is capable of performing simultaneously multiple address translation of logical addresses of different page sizes into corresponding physical addresses. The system includes a processor, a main storage area, which is logically partitioned into a number of partial spaces, and an address translation controller for translating logical addresses output by the processor to physical addresses which correspond to partial spaces of the main storage area.
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