Testability architecture and techniques for programmable interconnect architecture

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United States of America Patent

PATENT NO 5432441
SERIAL NO

08102381

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Abstract

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In an integrated circuit having a plurality of function modules, each of the function modules having at least two inputs and at least one output. The integrated circuit is user programmable such that interconnections between selected ones of the function modules and input/output pins on the integrated circuit may be made. The integrated circuit further having two states, a first unprogrammed state where none of the interconnections have been made, and a second, programmed state in which selected interconnections have been made. Circuitry for testing the functionality of individual ones of the function modules when the integrated circuit is in the unprogrammed state comprises addressing means for selecting any one of the function modules, data input means for providing a selected logic level to at least one of the inputs of the function module selected by the addressing means, and output-connecting means, responsive to the addressing means, for temporarily connecting the output of the selected one of the function modules to one of the input/output pins on the integrated circuit.

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Patent Owner(s)

Patent OwnerAddress
ACTEL CORPORATIONMOUNTAIN VIEW CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Jia-Hwang Cupertino, CA 18 581
El-Ayat, Khaled A Cupertino, CA 22 1977

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