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Abstract

An architecture for an optical computing apparatus which utilizes global free space smart optical interconnects and is based on a digital logic family derived from augmenting semiconductor technology with optical logic. The apparatus comprises input means, control means, and detector means, where the detector means includes means for detecting an optical input signal, electronically amplifying and selectively negating the detected signal, and providing an optical output signal. The architecture is capable of providing outputs which are Boolean logical AND/OR operations on designated combinations of binary input bits, and in another embodiment is capable of forming the combinatorial functionals and summations into which an arbitrary user instruction may be decomposed by means of Shannon's theorem and DeMorgan's laws.

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First Claim