Method and circuitry for minimizing clock-data skew in a bus system
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United States of America Patent
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Jul 11, 1995
Issued Date -
N/A
app pub date -
Jan 7, 1994
filing date -
Mar 6, 1992
priority date (Note) -
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Abstract
A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.
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