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Abstract

A method and apparatus for controlling memory access operations of a pipelined processor using a 'write queue' are described. The write queue temporarily stores addresses of writes not yet made in memory. Each write queue entry includes a write-read conflict bit. When an entry is first put into the write queue, the write-read conflict bit is cleared. When a subsequent memory read request occurs, the address of the read request is compared to the addresses stored in the write queue. If there is a match, the write-read conflict bit in the matching entry is set. If after this comparison no conflict bits are set, the read is allowed to proceed to memory before the queued writes. On the other hand, if any conflict bits are set, the read is prevented from proceeding. The conflict bits are cleared as the queued writes are performed in memory. Also, the write queue is able to accept additional entries while a read request is stalled. In a preferred arrangement, data-stream reads (D-reads) are given priority over instruction-stream reads (I-reads), and separate conflict bits are used to indicate D-read conflicts and I-read conflicts. In this fashion, the fetching of data and the fetching of instructions are stalled and resumed independently when conflicts arise.

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