US Patent No: 5,432,999

Number of patents in Portfolio can not be more than 2000

Integrated circuit lamination process

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Abstract

A process for forming a multi-layer integrated circuit utilizes a rigid substrate covered by a dissolvable material layer, which is in turn coated by a protective material layer. Electrically conductive posts and a semiconductive material layer are then sequentially formed on the protective material layer. An integrated circuit is formed in the top surface of the semiconductive material layer. Upper conductive pads are formed on exposed ends of the conductive posts. The substrate, dissolvable material layer and protective material layer support each thin integrated circuit layer during fabrication and are removed to enable the integrated circuits to be interconnected into a stack via the conductive posts and pads. In another embodiment, the rigid substrate is formed of a dissolvable material layer which is in turn coated by a protective, insulating layer. The conductive posts and integrated circuit are formed on the substrate prior to dissolving the substrate to expose top and bottom pads attached to opposite ends of the conductive posts. The top and bottom pads of a plurality of like integrated circuits are connected to provide interconnection of multiple dies in a stacked arrangement.

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First Claim

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Patent Owner(s)

  • Assignment data not available. Check USPTO

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Capps, David F 134 Moross, Mt. Clemens, MI 48043 6 246
Szwarc, Tyra M 17018 Kingsbrook, Clinton Township, Macomb County, MI 48038 1 88

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Patent Citation Ranking

Forward Cites

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