Dynamic random access memory system
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United States of America Patent
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Jul 18, 1995
Issued Date -
N/A
app pub date -
Nov 3, 1994
filing date -
Jun 2, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
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