Semiconductor memory device with reduced power consumption and reliable read mode operation
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United States of America Patent
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Jul 18, 1995
Grant Date -
N/A
app pub date -
Jul 6, 1994
filing date -
Jul 21, 1993
priority date (Note) -
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Abstract
A semiconductor memory device includes a memory cell array formed of a plurality of memory cells, a peripheral circuit supplied with address signals for selecting a memory cell in the memory cell array, the peripheral circuit further conducting a reading of the content of information stored in the selected memory cell and producing an output indicative thereof, and an address transition detection circuit for detecting a transition in any of the address signals and further for detecting a transition of the output of the peripheral circuit, wherein the address transition detection circuit activates the peripheral circuit when a transition has occurred in any of the address signals and the output of the peripheral circuit.
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