Deterministic timed bus access method

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United States of America Patent

PATENT NO 5434861
SERIAL NO

08192206

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Abstract

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An improved timed deterministic bus access method and system for a bidirectional linear bus, a unidirectional linear bus, a star and a tree type of bus structure. The method employs a master timing reference signal and discrete values of time delay at each node together with a cycle start signal to provide orderly deterministic access by a number of nodes to a shared bus structure. The master timing reference signal is generated by a polling node which can also transmit messages. The time delays in the nodes can correspond to their physical order from the polling node when this is located at one end. Alternatively values of timing delays can be chosen to make the physical location of the polling node of the other nodes unimportant. The method provides for prioritised access to the bus structure using a reservation hold.

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Patent Owner(s)

Patent OwnerAddress
STRATHCLYDE UNIVERSITY OF16 RICHMOND STREET MCCANCE BUILDING GLASGOW G1 1XQ

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Masson, Derek 18 Campsie Drive, Bearsden Glasgow, GB6 2 280
Pritty, David 66 Colpuhoun Street, Helensburgh, GB6 1 80

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