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Abstract

A fault tolerant memory system including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location has a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of the memory chips or a previously assigned spare chip in the event that a chip failure is identified. A memory maintenance facility for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.

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First Claim