Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
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United States of America Patent
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Jul 18, 1995
Grant Date -
N/A
app pub date -
Aug 6, 1990
filing date -
Aug 6, 1990
priority date (Note) -
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Abstract
A method for reading data from an n-way, set associative cache. n individually addressable memory units are provided, with each of the units storing a plurality of data elements. All n of the units are concurrently addressed to transfer a data element from each of the units to a respective latch, and one of such data elements is selectively transferred from one of the latches. The units are then serially addressed in a predetermined pattern to sequentially transfer data elements out of the units.
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