Semiconductor memory device with high dielectric capacitor structure

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United States of America Patent

PATENT NO 5436477
SERIAL NO

08262116

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Abstract

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Transfer gate transistors are formed on a main surface of a semiconductor substrate. The transfer gate transistors have impurity regions for serving as source/drain regions. A first interlayer insulating film having a substantially flat upper surface is formed to cover the transfer gate transistors. The first interlayer insulating film is provided with contact holes reaching the impurity regions. Plugs are formed in the contact holes. Capacitors are only formed on the flat upper surface of the first interlayer insulating film. Lower electrodes of the capacitors and the plugs are electrically connected with each other through barrier layers. Thus, it is possible to improve capacitances of capacitors in a DRAM.

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Patent Owner(s)

Patent OwnerAddress
MITSUBISHI DENKI KABUSHIKI KAISHA2-3 MARUNOUCHI 2-CHOME CHIYODA-KU TOKYO 100-8310

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hashizume, Yasushi Hyogo, JP 10 182
Shinkawata, Hiroki Hyogo, JP 34 352

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