Bit error reduction by using checksums in a switching network implemented as triplets
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United States of America Patent
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Jul 25, 1995
Grant Date -
N/A
app pub date -
Sep 30, 1992
filing date -
Sep 30, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for reducing bit error in a digital communications system including the step of identifying whether a data or information word was correctly switched through a network having at least three switching levels after the data word has been switched by undertaking a parity bit check as well as a bit by bit comparison of the bits in the data word, and an apparatus configured to perform the method. Bit errors are corrected either on the basis of majority decision or by a Statistical evaluation of the bit error rates of the various switching levels of the switching network.
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