Power multiplication circuit which reduces an offset voltage of a Hall element to zero
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United States of America Patent
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-
Aug 1, 1995
Grant Date -
N/A
app pub date -
Jul 30, 1993
filing date -
Dec 11, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A power multiplication circuit including a Hall element for generating between voltage output terminals thereof a first output voltage corresponding to a power of a system under measurement. The circuit further includes a voltage polarity detection circuit for detecting a polarity of a power source voltage of the system and an operating circuit connected to receive the first output voltage and the polarity for amplifying the first output voltage and for changing over between amplified first output voltage and an inverted voltage of the amplified first output voltage to generate a second output voltage in accordance with the polarity. The circuit also includes an integrating amplifier circuit for integrating the second output voltage to generate an integrated signal and a variable resistance element connected between one of the voltage output terminals of the Hall element and ground, and connected to receive the integrated signal. The resistance thereof is changed by the integrated signal so that an offset voltage of the Hall element is reduced to zero.
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