Importance

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Abstract

The synchronous memory (30) includes an address transition detection and control circuitry (42) which detects whether a net change in a selected portion of the address has occurred between consecutive active edges of the clock signal. If an address transition is detected, then a full memory cycle is initiated as usual. However, if no address transition is detected, the amount of activity performed in that memory cycle is reduced or modified to eliminate certain full memory cycle operations. In the reduced power memory cycle, the data already retained by the latches at the sense amplifiers (36) are accessed rather than accessing the memory array (32) for the same data.

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First Claim