Arbitration of packet switched busses, including busses for shared memory multiprocessors
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 8, 1995
Issued Date -
N/A
app pub date -
Apr 29, 1994
filing date -
Nov 30, 1990
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An arbiter is provided for resolving contention on synchronous packet switched busses, including busses composed of a plurality of pipelined segments, to ensure that all devices serviced by such a bus are given fair, bounded time access to the bus and to permit such devices to fill all available bus cycles with packets. Flow control for shared memory multiprocessors is readily implemented with this arbiter because the arbiter supports different types of arbitration requests and the prioritization of such arbitration requests by type.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully