Computer pipeline including dual-ported, content-addressable writebuffer
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United States of America Patent
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Aug 8, 1995
Issued Date -
N/A
app pub date -
Feb 9, 1994
filing date -
Jul 31, 1985
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Abstract
A high performance computer pipeline allows reading or writing of data during a single clock cycle. A write queue is provided for temporary buffering of data to be written back to memory. Data is transferred from the write queue to memory during otherwise unused memory access cycles.
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