Importance

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Abstract

An apparatus which converts burst mode bus cycles into single cycle mode cycles and converts separate address and data strobe signals into a single address strobe in a computer system. The apparatus also receives an address strobe signal, a number of address signals and the length of the burst when a device begins a burst cycle. After the first cycle of the burst transfer is complete, the apparatus initiates each subsequent cycle comprising the burst transfer by incrementing the address signals and providing additional address strobe signals until the burst is complete. The logic also facilitates address pipelining by monitoring a next address signal generated by the device. The apparatus monitors the separate address strobe and data strobe signals and generates the single address strobe signal on the next clock cycle after the address and data strobe signals are asserted. If only the address strobe signal is asserted at the beginning of a cycle, then the single address strobe signal is asserted only after valid data is available on the bus and the data strobe signal is asserted. The apparatus also monitors next address signals generated by the device to facilitate pipelining.

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First Claim