Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries

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United States of America Patent

PATENT NO 5441904
SERIAL NO

08341892

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Abstract

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A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film. This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH.sub.4 or Si.sub.2 H.sub.6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si.sub.2 H.sub.6 or SiH.sub.4, whichever one was not used to treat the first polysilicon layer, forming a tungsten silicide layer on the second polysilicon layer, and patterning the tungsten silicide layer, the second polysilicon layer and the first polysilicon layer by means of a mask etching process.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.OTTAWA ONTARIO, CA1400

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Jong C Seoul, KR 11 550
Woo, Sang H Kyungki-Do, KR 8 165

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
* 4354309 Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon 48 1980
 
UNITED MICROELECTRONICS CORP. (1)
* 5350698 Multilayer polysilicon gate self-align process for VLSI CMOS device 43 1993
 
RENESAS ELECTRONICS AMERICA INC. (1)
* 5093700 Single gate structure with oxide layer therein 17 1991
 
TEXAS INSTRUMENTS INCORPORATED (1)
* 4816425 Polycide process for integrated circuits 19 1987
 
KABUSHIKI KAISHA TOSHIBA (1)
* 5212105 Semiconductor device manufacturing method and semiconductor device manufactured thereby 5 1991
 
MOTOROLA, INC. (1)
* 4829024 Method of forming layered polysilicon filled contact by doping sensitive endpoint etching 68 1988
 
CANON KABUSHIKI KAISHA (1)
* 4868140 Semiconductor device and method of manufacturing the same 12 1988
* Cited By Examiner

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Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (4)
* 2003/0189,253 Methods for forming wordlines, transistor gates, and conductive interonnects, and wordline, transistor gate, and conductive interconnect structures 0 2001
* 2005/0156,240 Thin film transistors and semiconductor constructions 0 2004
* 2006/0261,421 Boron incorporated diffusion barrier material 0 2006
* 2008/0237,601 TRANSISTORS AND SEMICONDUCTOR CONSTRUCTIONS 2 2008
 
TOSHIBA MEMORY CORPORATION (3)
* 6362511 MIS-type semiconductor device having a multi-portion gate electrode 14 1999
* 8053776 Vertical diode and method for manufacturing same and semiconductor memory device 2 2009
* 2010/0163,821 VERTICAL DIODE AND METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR MEMORY DEVICE 2 2009
 
CYPRESS SEMICONDUCTOR CORPORATION (1)
* 5981364 Method of forming a silicon gate to produce silicon devices with improved performance 9 1995
 
CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD. (1)
* 5767004 Method for forming a low impurity diffusion polysilicon layer 85 1996
 
MICRON TECHNOLOGY, INC. (24)
6797601 Methods for forming wordlines, transistor gates, and conductive interconnects 1 1999
6730584 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures 7 1999
6635939 Boron incorporated diffusion barrier material 12 1999
6420275 System and method for analyzing a semiconductor surface 1 1999
6511900 Boron incorporated diffusion barrier material 10 2000
6630391 Boron incorporated diffusion barrier material 13 2001
6749715 System and method for analyzing a semiconductor surface 3 2001
6812530 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures 0 2001
* 6611032 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures 7 2001
6519031 Method for analyzing a semiconductor surface 4 2001
6602795 System and method for analyzing a semiconductor surface 1 2002
6699781 Conductive material for integrated circuit fabrication 0 2003
6911381 Boron incorporated diffusion barrier material 20 2003
7084504 Boron incorporated diffusion barrier material 4 2003
6908803 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures 5 2003
6906547 Conductive material for integrated circuit fabrication 0 2004
* 7385222 Thin film transistors and semiconductor constructions 3 2004
7271092 Boron incorporated diffusion barrier material 3 2005
* 7452760 Thin film transistors and semiconductor constructions 2 2006
* 7566907 Thin film transistors and semiconductor constructions 1 2008
* 7825414 Method of forming a thin film transistor 0 2008
* 2009/0047,776 Method of Forming a Thin Film Transistor 2 2008
* 2009/0302,322 Method of Forming a Thin Film Transistor 0 2009
* 2011/0024,762 Method of Forming a Thin Film Transistor 0 2010
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (6)
* 5652156 Layered polysilicon deposition method 36 1995
* 5840607 Method of forming undoped/in-situ doped/undoped polysilicon sandwich for floating gate application 39 1996
* 6780741 Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers 6 2003
* 7382028 Method for forming silicide and semiconductor device formed thereby 1 2005
* 2006/0231,910 Method for forming silicide and semiconductor device formed thereby 32 2005
* 2008/0128,835 Semiconductor Device Having a Random Grained Polysilicon Layer and a Method for its Manufacture 0 2007
 
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (2)
* 6489661 Method of manufacturing semiconductor device and semiconductor device 1 2001
* 6693341 Semiconductor device 0 2002
 
SAMSUNG ELECTRONICS CO., LTD. (2)
6451694 Control of abnormal growth in dichloro silane (DCS) based CVD polycide WSix films 1 2001
* 7557403 Double gate transistors having at least two polysilicon patterns on a thin body used as active region and methods of forming the same 0 2006
 
LG Semicon Co., Ltd. (1)
* 5712181 Method for the formation of polycide gate in semiconductor device 26 1995
 
TWITTER, INC. (2)
* 7714366 CMOS transistor with a polysilicon gate electrode having varying grain size 0 2004
* 2005/0110,096 CMOS TRANSISTOR WITH A POLYSILICON GATE ELECTRODE HAVING VARYING GRAIN SIZE 3 2004
 
UNITED MICROELECTRONICS CORP. (7)
* 5554566 Method to eliminate polycide peeling 29 1994
* 5877074 Method for improving the electrical property of gate in polycide structure 28 1997
* 6114196 Method of fabricating metal-oxide semiconductor transistor 2 1999
* 6069061 Method for forming polysilicon gate 7 1999
* 7358197 Method for avoiding polysilicon film over etch abnormal 1 2003
* 2005/0087,510 Method for avoiding polysilicon film over etch abnormal 2 2003
* 2008/0296,705 GATE AND MANUFACTURING METHOD OF GATE MATERIAL 0 2007
 
PS4 LUXCO S.A.R.L. (2)
* 6800543 Semiconductor device having a low-resistance gate electrode 12 2002
* 2003/0170,942 Semiconductor device having a low-resistance gate electrode 3 2002
 
RENESAS ELECTRONICS CORPORATION (1)
* 5639679 Method of manufacturing a semiconductor device comprising a non-volatile memory cell having a multi-layered floating gate 12 1995
 
KABUSHIKI KAISHA TOSHIBA (1)
* 5866930 Semiconductor device and method of manufacturing the same 25 1996
 
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION (1)
* 6277719 Method for fabricating a low resistance Poly-Si/metal gate 15 1999
 
MAGNACHIP SEMICONDUCTOR, LTD. (1)
* 5817547 Method for fabricating a metal oxide semiconductor field effect transistor having a multi-layered gate electrode 9 1996
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (2)
* 5639689 Method for fabricating storage electrode of semiconductor device 54 1994
* 5837600 Method for fabricating a semiconductor device 2 1996
 
NEC ELECTRONICS CORPORATION (1)
* 6297529 Semiconductor device with multilayered gate structure 7 1999
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
* 6670263 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 2 2001
* 6893948 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 1 2003
* 2004/0023,476 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 1 2003
 
POLARIS INNOVATIONS LIMITED (1)
* 7153781 Method to etch poly Si gate stacks with raised STI structure 2 2003
 
TESSERA ADVANCED TECHNOLOGIES, INC. (2)
* 6521943 Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture 18 2000
6723625 Semiconductor device having thin electrode laye adjacent gate insulator and method of manufacture 2 2002
 
U.S. BANK NATIONAL ASSOCIATION (2)
* 2004/0082,156 Boron incorporated diffusion barrier material 1 2003
* 2004/0080,002 Boron incorporated diffusion barrier material 0 2003
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
* 6194296 Method for making planarized polycide 4 1995
 
GLOBALFOUNDRIES INC. (2)
* 9472402 Methods and structures for protecting one area while processing another area on a chip 0 2014
* 2015/0004,802 Methods and Structures for Protecting One Area While Processing Another Area on a Chip 1 2014
 
FUJI ELECTRIC CO., LTD. (1)
* 5618755 Method of manufacturing a polycide electrode 9 1995
 
MACRONIX INTERNATIONAL CO., LTD. (1)
* 2004/0209,467 METHOD FOR REDUCING PLASMA RELATED DAMAGES 0 2003
 
INTEL CORPORATION (2)
6703672 Polysilicon/amorphous silicon composite gate electrode 8 1997
* 6017819 Method for forming a polysilicon/amorphous silicon composite gate electrode 13 1997
 
STMICROELECTRONICS S.R.L. (3)
* 6087228 Method of making a nonvolatile memory cell using EPROM mask and ROM processing steps 0 1997
* 7199028 Method for manufacturing semiconductor device 0 2003
* 2004/0266,212 Method for manufacturing semiconductor device 0 2003
 
LONGITUDE SEMICONDUCTOR S.A.R.L. (2)
* 7078777 Semiconductor device having a low-resistance gate electrode 0 2004
* 2005/0020,045 Semiconductor device having a low-resistance gate electrode 0 2004
 
PROMOS TECHNOLOGIES INC. (1)
* 6117755 Method for planarizing the interface of polysilicon and silicide in a polycide structure 6 1998
 
APTINA IMAGING CORPORATION (7)
6329670 Conductive material for integrated circuit fabrication 9 1999
6646456 Conductive material for integrated circuit fabrication 0 2001
6518181 Conductive material for integrated circuit fabrication 0 2001
6870380 Conductive material for integrated circuit fabrication 0 2003
6781365 Conductive material for integrated circuit fabrication 1 2003
6765398 Conductive material for integrated circuit fabrication 1 2003
7046029 Conductive material for integrated circuit fabrication 0 2005
* Cited By Examiner