Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries

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United States of America Patent

PATENT NO 5441904
SERIAL NO

08341892

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Abstract

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A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film. This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH.sub.4 or Si.sub.2 H.sub.6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si.sub.2 H.sub.6 or SiH.sub.4, whichever one was not used to treat the first polysilicon layer, forming a tungsten silicide layer on the second polysilicon layer, and patterning the tungsten silicide layer, the second polysilicon layer and the first polysilicon layer by means of a mask etching process.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.OTTAWA ONTARIO, CA1363

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Jong C Seoul, KR 11 583
Woo, Sang H Kyungki-Do, KR 8 167

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