PLD with selective inputs from local and global conductors
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United States of America Patent
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Aug 22, 1995
Grant Date -
N/A
app pub date -
Jul 8, 1993
filing date -
Jul 8, 1993
priority date (Note) -
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Abstract
A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.
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