Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals
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United States of America Patent
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Aug 22, 1995
Grant Date -
N/A
app pub date -
Mar 31, 1994
filing date -
Apr 2, 1993
priority date (Note) -
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Importance
Abstract
A synchronous dynamic random access memory device latches external command signals for defining the internal sequence, and an input circuit produces an internal control signal from a system clock signal and a clock enable signal for latching the external command signals, wherein the input circuit maintains the internal control signal in an active level for a predetermined time period regardless of the duty ratio of the external clock signal so that a malfunction hardly takes place.
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