Developing method and apparatus of hierarchical graphic data for use in a semiconductor integrated circuit
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United States of America Patent
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Aug 29, 1995
Grant Date -
N/A
app pub date -
Jan 31, 1994
filing date -
Mar 19, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and apparatus for using hierarchically organized data to design semiconductor integrated circuits is herein disclosed wherein a plurality of macros and circuit logic cells containing circuit component parameter information are cross referenced using two types of pointers. An intermediate table 27 in a logic development file 5 stores information relating to a general controlling macro 'CHIP', user defined macros A, B, and also stores the parameter information relating to every macro. A cell table 28 stores circuit cells C, D, E, F. The macro 'CHIP' A, B, and cells, and the macro and cell are cross referenced by multi-table and an identical table pointer.
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