US Patent No: 5,446,696

Number of patents in Portfolio can not be more than 2000

Method and apparatus for implementing refresh in a synchronous DRAM system

1 Status Updates

Stats

ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1206

International Classification(s)

  • International Classification not provided for expired patents

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dillon, John B Palo Alto, CA 42 1656
Farmwald, Michael P Portola Valley, CA 10 557
Gasbarro, James A Mountain View, CA 39 1604
Griffin, Matthew M Mountain View, CA 13 429
Horowitz, Mark A Menlo Park, CA 137 2934
Ware, Frederick A Los Altos Hills, CA 307 2516

Cited Art

Patent Info (Count) # Cites Year
 
NCR CORPORATION (2)
4,249,247 Refresh system for dynamic RAM memory 64 1979
4,631,701 Dynamic random access memory refresh control system 40 1983
 
CASIO COMPUTER CO., LTD. (1)
4,881,205 Compact electronic apparatus with a refresh unit for a dynamic type memory 71 1988
 
INTEL CORPORATION (1)
4,453,237 Multiple bit output dynamic random-access memory 14 1983
 
INTERNATIONAL COMPUTERS LIMITED (1)
4,901,283 Dynamic random-access memory system with power-up and power-down refresh circuits 47 1988
 
KABUSHIKI KAISHA TOSHIBA (1)
4,682,306 Self-refresh control circuit for dynamic semiconductor memory device 22 1985
 
NEC CORPORATION (1)
4,716,551 Semiconductor memory device with variable self-refresh cycle 65 1984
 
NIPPON ELECTRIC CO., LTD. (1)
4,393,477 Temperature responsive refresh control circuit 12 1980
 
ROUND ROCK RESEARCH, LLC (1)
5,262,998 Dynamic random access memory with operational sleep mode 69 1991
 
TEXAS INSTRUMENTS INCORPORATED (1)
4,459,660 Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU 24 1981

Patent Citation Ranking

  • Citation Ranking not provided for expired patents

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (57)
5,627,791 Multiple bank memory with auto refresh to specified bank 187 1996
6,115,318 Clock vernier adjustment 71 1996
5,923,611 Memory having a plurality of external clock signal inputs 54 1996
6,912,680 Memory system with dynamic timing correction 34 1997
5,940,608 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 110 1997
5,920,518 Synchronous clock generator including delay-locked loop 112 1997
5,956,289 Clock signal from an adjustable oscillator for an integrated circuit 64 1997
5,875,142 Integrated circuit with temperature detector 78 1997
6,173,432 Method and apparatus for generating a sequence of clock signals 92 1997
5,953,284 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 82 1997
6,011,732 Synchronous clock generator including a compound delay-locked loop 201 1997
5,940,609 Synchronous clock generator including a false lock detector 97 1997
5,926,047 Synchronous clock generator including a delay-locked loop signal loss detector 67 1997
6,101,197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 134 1997
5,930,198 Memory having a plurality of external clock signal inputs 10 1997
5,886,948 Memory having a plurality of external clock signal inputs 37 1997
6,269,451 Method and apparatus for adjusting data timing by delaying clock signal 43 1998
6,016,282 Clock vernier adjustment 215 1998
6,338,127 Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same 59 1998
6,349,399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 15 1998
6,279,090 Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device 21 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 318 1998
6,430,696 Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same 140 1998
6,374,360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 32 1998
6,002,627 Integrated circuit with temperature detector 67 1999
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 145 1999
6,201,424 Synchronous clock generator including a delay-locked loop signal loss detector 27 1999
6,340,904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 26 1999
6,119,242 Synchronous clock generator including a false lock detector 33 1999
6,160,755 Clock signal from an adjustable oscillator for an integrated circuit 73 1999
6,378,079 Computer system having memory device with adjustable data clocking 66 2000
6,327,196 Synchronous memory device having an adjustable data clocking circuit 53 2000
6,959,016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 13 2000
6,954,097 Method and apparatus for generating a sequence of clock signals 7 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 52 2001
6,499,111 Apparatus for adjusting delay of a clock signal relative to a data signal 42 2001
6,477,675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2001
6,952,462 Method and apparatus for generating a phase dependent control signal 21 2001
6,662,304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 125 2002
6,643,789 Computer system having memory device with adjustable data clocking using pass gates 17 2002
6,931,086 Method and apparatus for generating a phase dependent control signal 12 2002
7,016,451 Method and apparatus for generating a phase dependent control signal 4 2002
6,647,523 Method for generating expect data from a captured bit pattern, and memory device using same 12 2002
7,168,027 Dynamic synchronization of data capture on an optical or other high speed communications link 11 2003
7,085,975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 4 2003
7,159,092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 4 2003
7,583,551 Power management control and controlling memory refresh operations 1 2004
7,415,404 Method and apparatus for generating a sequence of clock signals 3 2005
7,418,071 Method and apparatus for generating a phase dependent control signal 7 2005
7,373,575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2006
8,181,092 Dynamic synchronization of data capture on an optical or other high speed communications link 0 2006
7,889,593 Method and apparatus for generating a sequence of clock signals 0 2007
7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2008
7,602,876 Method and apparatus for generating a phase dependent control signal 5 2008
8,107,580 Method and apparatus for generating a phase dependent control signal 1 2009
7,954,031 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 0 2009
8,433,023 Method and apparatus for generating a phase dependent control signal 0 2012
 
RAMBUS INC. (14)
6,513,103 Method and apparatus for adjusting the performance of a synchronous memory system 15 1997
6,021,076 Apparatus and method for thermal regulation in memory subsystems 26 1998
6,373,768 Apparatus and method for thermal regulation in memory subsystems 38 1999
6,343,042 DRAM core refresh with reduced spike current 36 2000
6,266,292 DRAM core refresh with reduced spike current 37 2000
6,310,814 Rambus DRAM (RDRAM) apparatus and method for performing refresh operations 51 2000
6,553,452 Synchronous memory device having a temperature register 11 2002
6,597,616 DRAM core refresh with reduced spike current 33 2002
7,149,856 Method and apparatus for adjusting the performance of a synchronous memory system 0 2003
6,778,458 Dram core refresh with reduced spike current 5 2003
7,142,475 Memory device having a configurable oscillator for refresh operation 6 2004
7,349,279 Memory Device Having a Configurable Oscillator for Refresh Operation 0 2006
7,337,294 Method and apparatus for adjusting the performance of a synchronous memory system 0 2006
8,296,540 Method and apparatus for adjusting the performance of a synchronous memory system 0 2008
 
KABUSHIKI KAISHA TOSHIBA (8)
6,018,491 Synchronous dynamic random access memory 2 1997
6,144,615 Synchronous dynamic random access memory 5 1999
6,377,503 Synchronous dynamic random access memory 2 2000
6,487,142 Synchronous dynamic random access memory 3 2001
6,646,955 Synchronous dynamic random access memory 2 2002
6,816,433 Synchronous dynamic random access memory for burst read/write operations 1 2003
6,928,028 Synchronous dynamic random access memory for burst read/write operations 1 2004
7,120,078 Synchronous semiconductor memory 2 2004
 
MICRON TECHNOLOGY, INC. (8)
6,453,377 Computer including optical interconnect, memory unit, and method of assembling a computer 52 1998
6,519,658 Memory unit and method of assembling a computer 14 2002
6,715,018 Computer including installable and removable cards, optical interconnection between cards, and method of assembling a computer 108 2002
6,662,243 Memory unit, a method of assembling a memory unit, a method of reconfiguring a system, and a memory device 0 2003
6,952,744 Computer including optical interconnect, memory unit, and method of assembling a computer 2 2003
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
 
MOSAID TECHNOLOGIES INCORPORATED (7)
5,946,244 Delay-locked loop with binary-coupled capacitor 121 1997
6,400,641 Delay-locked loop with binary-coupled capacitor 3 1999
6,262,921 Delay-locked loop with binary-coupled capacitor 46 2000
6,256,259 Delay-locked loop with binary-coupled capacitor 0 2000
6,483,757 Delay-locked loop with binary-coupled capacitor 1 2001
6,490,224 Delay-locked loop with binary-coupled capacitor 9 2001
6,490,207 Delay-locked loop with binary-coupled capacitor 22 2001
 
RENESAS ELECTRONICS CORPORATION (7)
5,673,398 Data transfer control method, and peripheral circuit, data processor and data processing system for the method 22 1995
5,978,891 Memory for operating synchronously with clock signals generated internally responsive to externally received control signals while outputting the clock signals via an external terminal 6 1997
6,247,073 Memory outputting both data and timing signal with output data and timing signal being aligned with each other 6 1999
6,088,743 Processor receiving response request corresponding to access clock signal with buffer for external transfer synchronous to response request and internal transfer synchronous to operational clock 14 1999
6,643,720 Data transfer control method, and peripheral circuit, data processor and data processing system for the method 1 2002
6,598,099 Data transfer control method, and peripheral circuit, data processor and data processing system for the method 2 2002
7,203,809 Data transfer control method, and peripheral circuit, data processor and processing system for the method 1 2005
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (2)
5,790,468 Refresh counter for synchronous dynamic random access memory and method of testing the same 5 1997
6,038,196 Semiconductor memory device having a synchronous DRAM 14 1998
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
6,389,505 Restore tracking system for DRAM 26 1998
8,244,972 Optimizing EDRAM refresh rates in a high performance cache architecture 0 2010
 
SAMSUNG ELECTRONICS CO., LTD. (2)
6,226,755 Apparatus and method for enhancing data transfer to or from a SDRAM system 27 1999
7,248,527 Self refresh period control circuits 14 2005
 
ANALOG DEVICES, INC. (1)
6,389,497 DRAM refresh monitoring and cycle accurate distributed bus arbitration in a multi-processing environment 7 1999
 
APPLE INC. (1)
5,771,180 Real time clock and method for providing same 14 1994
 
DELL USA, L.P. (1)
6,357,018 Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system 50 1999
 
ENHANCED MEMORY SYSTEMS, INC. (1)
7,453,752 Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder 1 2005
 
FREESCALE SEMICONDUCTOR, INC. (1)
6,862,240 Variable refresh control for a memory 40 2004
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
7,305,518 Method and system for dynamically adjusting DRAM refresh rate 2 2004
 
INTELLECTUAL VENTURES I LLC (1)
7,688,662 Method for hiding a refresh in a pseudo-static memory 2 2008
 
NEC ELECTRONICS CORPORATION (1)
5,566,119 Synchronous DRAM performing refresh operation a plurality of times in response to each refresh request command 13 1995
 
NVIDIA CORPORATION (1)
7,761,191 Management of operation of an integrated circuit 0 2006
 
SILICON LABORATORIES INC. (1)
7,502,883 USB integrated module 0 2003
 
SYMANTEC OPERATING CORPORATION (1)
7,831,769 System and method for performing online backup and restore of volume configuration information 1 2007
 
XEROX CORPORATION (1)
6,088,761 Reduced pin system interface 8 1997
 
XIONICS DOCUMENT TECHNOLOGIES, INC. (1)
5,894,586 System for providing access to memory in which a second processing unit is allowed to access memory during a time slot assigned to a first processing unit 12 1997