US Patent No: 5,448,165

Number of patents in Portfolio can not be more than 2000

Electrically tested and burned-in semiconductor die and method for producing same

Stats

ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

A semiconductor die is temporarily enclosed in a package. The packaged die is then electrically tested and burned in. The tested die is then removed from the package. If the die performed acceptably during test and burn-in, the die is retained and either used in a production integrated circuit or sold as an unpackaged individual die. The method is simple, inexpensive, and provides semiconductor dice of high reliability (packaged die yields approach 100%). Existing test and production facilities, equipment and process flows may be used with, at most, minor changes to process a semiconductor die for any application. Semiconductor dice processed by the method are particularly useful for complex and/or costly packaging options, e.g., multichip modules, hybrid circuits or chip-on-board.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEGRATED DEVICE TECHNOLOGY, INC.SAN JOSE, CA817

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hodge, Robin H Portola Valley, CA 4 167
Templeton, Jr Thomas H Fremont, CA 15 349

Cited Art

Patent Info (Count) # Cites Year
 
FREESCALE SEMICONDUCTOR, INC. (1)
4,985,988 Method for assembling, testing, and packaging integrated circuits 64 1989
 
HITACHI CHEMICAL COMPANY, LTD. (1)
5,120,665 Method of using an anisotropically electroconductive adhesive having pressure-deformable electroconductive particles to electrically connect circuits 102 1991
 
INTEGRATED SYSTEM ASSEMBLIES CORPORATION, A CORP. OF DE (1)
5,149,662 Methods for testing and burn-in of integrated circuit chips 79 1992
 
LOCKHEED MARTIN CORPORATION (1)
4,866,508 Integrated circuit packaging configuration for rapid customized design and unique test capability 87 1986
 
RELIABILITY INCORPORATED (1)
4,351,108 Packaging system for semiconductor burn-in 10 1980
 
ROUND ROCK RESEARCH, LLC (1)
5,173,451 Soft bond for semiconductor dies 41 1992

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (57)
5,807,762 Multi-chip module system and method of fabrication 40 1996
5,894,218 Method and apparatus for automatically positioning electronic dice within component packages 63 1996
6,008,538 Method and apparatus providing redundancy for fabricating highly reliable memory modules 41 1996
6,064,194 Method and apparatus for automatically positioning electronic dice within component packages 19 1996
6,060,339 Method and apparatus providing redundancy for fabricating highly reliable memory modules 37 1997
5,959,310 Multi-chip module system 22 1997
6,085,962 Wire bond monitoring system for layered packages 14 1997
6,395,565 Multi-chip module system and method of fabrication 20 1998
6,153,929 Low profile multi-IC package connector 22 1998
6,214,716 Semiconductor substrate-based BGA interconnection and methods of farication same 69 1998
5,955,877 Method and apparatus for automatically positioning electronic dice within component packages 14 1998
6,353,312 Method for positioning a semiconductor die within a temporary package 1 1999
6,815,251 High density modularity for IC's 25 1999
6,087,676 Multi-chip module system 22 1999
6,210,984 Method and apparatus for automatically positioning electronic dice within component packages 10 1999
6,150,828 Method and apparatus for automatically positioning electronic dice with component packages 7 1999
6,445,063 Method of forming a stack of packaged memory die and resulting apparatus 12 1999
6,215,181 Method and apparatus providing redundancy for fabricating highly reliable memory modules 33 1999
6,225,689 Low profile multi-IC chip package connector 109 2000
6,329,221 Method of forming a stack of packaged memory die and resulting apparatus 7 2000
6,646,286 Semiconductor substrate-based BGA interconnection 12 2000
6,599,822 Methods of fabricating semiconductor substrate-based BGA interconnection 7 2000
6,492,187 Method for automatically positioning electronic die within component packages 8 2000
6,274,390 Method and apparatus providing redundancy for fabricating highly reliable memory modules 3 2000
6,475,831 Methods for a low profile multi-IC chip package connector 5 2001
6,545,498 Method for in-line testing of flip-chip semiconductor assemblies 2 2001
6,531,772 Electronic system including memory module with redundant memory capability 29 2001
6,362,519 Low profile multi-IC chip package connector 3 2001
6,465,275 Method of forming a stack of packaged memory die and resulting apparatus 8 2001
6,841,868 Memory modules including capacity for additional memory 36 2001
7,166,915 Multi-chip module system 1 2001
6,486,546 Low profile multi-IC chip package connector 13 2002
6,677,671 Apparatus for forming a stack of packaged memory dice 0 2002
6,656,767 Method of forming a stack of packaged memory dice 11 2002
6,773,955 Low profile multi-IC chip package connector 6 2002
6,686,655 Low profile multi-IC chip package connector 5 2002
6,720,652 Apparatus providing redundancy for fabricating highly reliable memory modules 39 2002
6,750,070 Process for manufacturing flip-chip semiconductor assembly 0 2002
7,061,092 High-density modularity for ICS 8 2002
6,740,578 Methods of fabricating semiconductor substrate-based BGA interconnections 1 2002
6,900,459 Apparatus for automatically positioning electronic dice within component packages 7 2002
6,954,081 Method for in-line testing of flip-chip semiconductor assemblies 0 2003
7,061,109 Semiconductor substrate-based BGA interconnection for testing semiconductor devices 1 2003
6,897,553 Apparatus for forming a stack of packaged memory dice 8 2003
6,884,654 Method of forming a stack of packaged memory dice 2 2003
6,972,200 Method for manufacturing flip-chip semiconductor assembly 1 2003
7,074,648 Method for packaging flip-chip semiconductor assemblies 0 2003
6,967,113 Method for in-line testing of flip-chip semiconductor assemblies 0 2003
7,126,224 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements 1 2004
7,005,878 Method for in-line testing of flip-chip semiconductor assemblies 1 2004
6,982,177 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6,962,826 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6,953,699 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6,949,943 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6,953,700 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
7,091,061 Method of forming a stack of packaged memory dice 4 2005
7,105,366 Method for in-line testing of flip-chip semiconductor assemblies 1 2005
 
CHIP SUPPLY, INC. (1)
5,677,203 Method for providing known good bare semiconductor die 14 1995
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
6,560,839 Method for using a moisture-protective container 6 1997
 
IXYS CORPORATION (1)
5,654,896 Performance prediction method for semiconductor power modules and ICS 10 1994
 
KYOEI SANGYO CO., LTD. (1)
6,512,392 Method for testing semiconductor devices 43 2000
 
NETLOGIC MICROSYSTEMS, INC. (1)
7,304,875 Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same 3 2005
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,836,071 Method to produce known good die using temporary wire bond, die attach and packaging 13 1996
 
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMY (1)
5,781,791 Digital microelectronic circuit package using buffer dies and programmable device or memory dies 0 1996