Electrically tested and burned-in semiconductor die and method for producing same

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5448165
SERIAL NO

08001884

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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A semiconductor die is temporarily enclosed in a package. The packaged die is then electrically tested and burned in. The tested die is then removed from the package. If the die performed acceptably during test and burn-in, the die is retained and either used in a production integrated circuit or sold as an unpackaged individual die. The method is simple, inexpensive, and provides semiconductor dice of high reliability (packaged die yields approach 100%). Existing test and production facilities, equipment and process flows may be used with, at most, minor changes to process a semiconductor die for any application. Semiconductor dice processed by the method are particularly useful for complex and/or costly packaging options, e.g., multichip modules, hybrid circuits or chip-on-board.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEGRATED DEVICE TECHNOLOGY, INC.SAN JOSE, CA811

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hodge, Robin H Portola Valley, CA 4 178
Templeton, Jr Thomas H Fremont, CA 15 423

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (1)
* 5173451 Soft bond for semiconductor dies 42 1992
 
Integrated System Assemblies Corporation (1)
* 5149662 Methods for testing and burn-in of integrated circuit chips 100 1992
 
FREESCALE SEMICONDUCTOR, INC. (1)
* 4985988 Method for assembling, testing, and packaging integrated circuits 87 1989
 
RELIABILITY INCORPORATED (1)
* 4351108 Packaging system for semiconductor burn-in 11 1980
 
LOCKHEED MARTIN CORPORATION (1)
* 4866508 Integrated circuit packaging configuration for rapid customized design and unique test capability 88 1986
 
ZEAGEN, INC. (1)
* 5120665 Method of using an anisotropically electroconductive adhesive having pressure-deformable electroconductive particles to electrically connect circuits 108 1991
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (10)
* 2003/0132,776 Method for in-line testing of flip-chip semiconductor assemblies 0 2003
* 2004/0080,332 Method for manufacturing flip-chip semiconductor assembly 1 2003
* 2004/0168,316 Low profile multi-IC chip package connector 0 2004
* 2004/0212,092 Methods of fabricating semiconductor substrate-based BGA interconnections 0 2004
* 2004/0263,196 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
* 2004/0263,195 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
* 2004/0263,197 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
* 2006/0252,180 Method for a low profile multi-IC chip package connector 8 2006
* 2007/0262,463 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements 1 2006
* 2008/0003,712 Methods of making semiconductor fuses 1 2006
 
SEIKO EPSON CORPORATION (1)
* 2009/0035,929 Method of manufacturing semiconductor device 1 2007
 
U.S. BANK NATIONAL ASSOCIATION (1)
* 2004/0026,791 Apparatus for forming a stack of packaged memory dice 7 2003
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
6560839 Method for using a moisture-protective container 6 1997
 
IXYS CORPORATION (1)
* 5654896 Performance prediction method for semiconductor power modules and ICS 12 1994
 
MICRON TECHNOLOGY, INC. (57)
* 5807762 Multi-chip module system and method of fabrication 50 1996
* 5894218 Method and apparatus for automatically positioning electronic dice within component packages 72 1996
* 6008538 Method and apparatus providing redundancy for fabricating highly reliable memory modules 45 1996
* 6064194 Method and apparatus for automatically positioning electronic dice within component packages 26 1996
* 6060339 Method and apparatus providing redundancy for fabricating highly reliable memory modules 37 1997
* 5959310 Multi-chip module system 25 1997
* 6085962 Wire bond monitoring system for layered packages 14 1997
6395565 Multi-chip module system and method of fabrication 23 1998
* 6153929 Low profile multi-IC package connector 25 1998
6214716 Semiconductor substrate-based BGA interconnection and methods of farication same 83 1998
* 5955877 Method and apparatus for automatically positioning electronic dice within component packages 15 1998
6353312 Method for positioning a semiconductor die within a temporary package 2 1999
6815251 High density modularity for IC's 35 1999
* 6087676 Multi-chip module system 25 1999
6210984 Method and apparatus for automatically positioning electronic dice within component packages 10 1999
* 6150828 Method and apparatus for automatically positioning electronic dice with component packages 7 1999
6445063 Method of forming a stack of packaged memory die and resulting apparatus 13 1999
6215181 Method and apparatus providing redundancy for fabricating highly reliable memory modules 33 1999
6225689 Low profile multi-IC chip package connector 156 2000
6329221 Method of forming a stack of packaged memory die and resulting apparatus 8 2000
6646286 Semiconductor substrate-based BGA interconnection 13 2000
6599822 Methods of fabricating semiconductor substrate-based BGA interconnection 7 2000
6492187 Method for automatically positioning electronic die within component packages 9 2000
6274390 Method and apparatus providing redundancy for fabricating highly reliable memory modules 3 2000
6475831 Methods for a low profile multi-IC chip package connector 5 2001
* 6545498 Method for in-line testing of flip-chip semiconductor assemblies 2 2001
6531772 Electronic system including memory module with redundant memory capability 29 2001
6362519 Low profile multi-IC chip package connector 3 2001
6465275 Method of forming a stack of packaged memory die and resulting apparatus 9 2001
6841868 Memory modules including capacity for additional memory 36 2001
7166915 Multi-chip module system 1 2001
6486546 Low profile multi-IC chip package connector 25 2002
6677671 Apparatus for forming a stack of packaged memory dice 1 2002
6656767 Method of forming a stack of packaged memory dice 25 2002
6773955 Low profile multi-IC chip package connector 7 2002
6686655 Low profile multi-IC chip package connector 22 2002
6720652 Apparatus providing redundancy for fabricating highly reliable memory modules 39 2002
6750070 Process for manufacturing flip-chip semiconductor assembly 0 2002
7061092 High-density modularity for ICS 55 2002
6740578 Methods of fabricating semiconductor substrate-based BGA interconnections 3 2002
6900459 Apparatus for automatically positioning electronic dice within component packages 13 2002
6954081 Method for in-line testing of flip-chip semiconductor assemblies 0 2003
7061109 Semiconductor substrate-based BGA interconnection for testing semiconductor devices 2 2003
6897553 Apparatus for forming a stack of packaged memory dice 8 2003
6884654 Method of forming a stack of packaged memory dice 2 2003
6972200 Method for manufacturing flip-chip semiconductor assembly 1 2003
7074648 Method for packaging flip-chip semiconductor assemblies 1 2003
6967113 Method for in-line testing of flip-chip semiconductor assemblies 0 2003
7126224 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements 3 2004
7005878 Method for in-line testing of flip-chip semiconductor assemblies 1 2004
6982177 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6962826 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6953699 Method for in-line testing of flip-chip semiconductor assemblies 1 2004
6949943 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
6953700 Method for in-line testing of flip-chip semiconductor assemblies 0 2004
7091061 Method of forming a stack of packaged memory dice 6 2005
7105366 Method for in-line testing of flip-chip semiconductor assemblies 2 2005
 
Kyoei Sangyo Co., Ltd. (1)
* 6512392 Method for testing semiconductor devices 77 2000
 
Chip Supply, Inc. (1)
* 5677203 Method for providing known good bare semiconductor die 15 1995
 
TEXAS INSTRUMENTS INCORPORATED (1)
* 5836071 Method to produce known good die using temporary wire bond, die attach and packaging 14 1996
 
The United States of America as represented by the Secretary of the Army (1)
* 5781791 Digital microelectronic circuit package using buffer dies and programmable device or memory dies 0 1996
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
7304875 Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same 12 2005
* Cited By Examiner