Frame buffer with matched frame rate
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United States of America Patent
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Sep 5, 1995
Grant Date -
N/A
app pub date -
Jul 18, 1991
filing date -
Jul 18, 1991
priority date (Note) -
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Abstract
A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.
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