US Patent No: 5,448,522

Number of patents in Portfolio can not be more than 2000

Multi-port memory emulation using tag registers

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Abstract

A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CADENCE DESIGN SYSTEMS, INC.SAN JOSE, CA1294

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Thomas B San Jose, CA 17 523

Cited Art

Patent Info (Count) # Cites Year
 
OKI SEMICONDUCTOR CO., LTD. (1)
5,148,397 Semiconductor memory with externally controlled dummy comparator 8 1991

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (11)
5,680,583 Method and apparatus for a trace buffer in an emulation system 66 1994
5,819,065 System and method for emulating memory 37 1996
5,822,564 Checkpointing in an emulation system 25 1996
5,841,967 Method and apparatus for design verification using emulation and simulation 66 1996
5,920,712 Emulation system having multiple emulator clock cycles per emulated clock cycle 44 1996
5,884,066 Method and apparatus for a trace buffer in an emulation system 17 1997
5,960,191 Emulation system with time-multiplexed interconnect 74 1997
5,970,240 Method and apparatus for configurable memory emulation 45 1997
5,940,603 Method and apparatus for emulating multi-ported memory circuits 47 1997
6,058,492 Method and apparatus for design verification using emulation and simulation 31 1998
6,377,912 Emulation system with time-multiplexed interconnect 60 1999
 
ALTERA CORPORATION (8)
6,028,808 Programmable logic array integrated circuits 4 1997
6,467,017 Programmable logic device having embedded dual-port random access memory configurable as single-port memory 39 1998
6,023,439 Programmable logic array integrated circuits 4 1998
6,018,490 Programmable logic array integrated circuits 8 1998
6,134,173 Programmable logic array integrated circuits 59 1998
6,191,998 Programmable logic device memory array circuit having combinable single-port memory arrays 58 1999
7,111,110 Versatile RAM for programmable logic device 10 2002
7,480,763 Versatile RAM for a programmable logic device 0 2006
 
VERISITY DESIGN, INC. (4)
6,421,251 Array board interconnect system and method 26 1998
6,134,516 Simulation server system and method 84 1998
6,026,230 Memory simulation system and method 72 1998
6,389,379 Converification system and method 120 1998
 
VERSITY DESIGN, INC. (2)
6,009,256 Simulation/emulation system and method 101 1997
6,321,366 Timing-insensitive glitch-free logic system and method 102 1998
 
XILINX, INC. (2)
5,566,123 Synchronous dual port ram 70 1995
5,631,577 Synchronous dual port RAM 56 1996
 
ARKOS, INC. (1)
5,923,865 Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing 10 1995