Boundary scan architecture extension
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United States of America Patent
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Sep 5, 1995
Grant Date -
N/A
app pub date -
Oct 29, 1992
filing date -
Oct 29, 1992
priority date (Note) -
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Abstract
A method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.
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