Structure and method for configuration of a field programmable gate array
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United States of America Patent
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Sep 12, 1995
Grant Date -
N/A
app pub date -
Oct 7, 1994
filing date -
Oct 7, 1994
priority date (Note) -
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Abstract
A structure and method for configuring a field programmable gate array (FPGA). A configuration memory cell within the FPGA receives a programming signal. In response, the configuration memory cell provides a signal to a configuration control circuit to configure the FPGA. The configuration memory cell includes an input lead, a storage device and a selectable configuration circuit. The input lead carries the programming signal to the storage device. The storage device stores the programming signal and an inverted programming signal which is the inverse of the programming signal. The selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to a first input lead of the configuration control circuit. The configuration control circuit couples (or decouples) various elements of the FPGA in response to the signal provided on the first input lead. In an alternate embodiment, the selectable configuration circuit is coupled between the input lead and the storage device. Again, the selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to the first input lead of the configuration control circuit.
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