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Abstract

A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU) connected to system memory by a first system bus, and a second system bus connected to the CPU; (ii) a host bridge connecting the second system bus to a peripheral bus; (iii) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto; and (v) arbitration logic which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

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First Claim