Sequential pipelined processing for the compression and decompression of image data
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United States of America Patent
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Sep 12, 1995
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N/A
app pub date -
Jun 4, 1992
filing date -
Jun 4, 1992
priority date (Note) -
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Abstract
A sequential process-pipeline has a first processing stage (30) coupled to a CODEC (24) through a plurality of buffers, including an image data input buffer (28), an image data output buffer (26), and an address buffer (34). The image data input buffer stores, for each block of image data, control information for controlling the processing of an associated block of image data. The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory (22). A local controller (18) is responsive to the writing of an address into the address buffer to read the control information for a block to be processed, and to initiate the operation of the CODEC, in accordance with the read-out information, to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.
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