US Patent No: 5,452,227

Number of patents in Portfolio can not be more than 2000

Method and apparatus for converting a programmable logic device designed into a selectable target gate array design

Stats

ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

The present invention is a translation system that translates a definition of a prototyped programmable device defined in a programmable device specification into a generic behavioral model of the device and into lists of logic blocks and connections for implementing the device as a non-programmable device in an application specific target technology. The lists and behavioral models are used to create command files that drive logic synthesis and network connection list processing operations to generate a generic list of logic and network connections. The generic list and commands are used to create device test vectors for testing the behavior of the model and the target device design. The target technology lists and command files are processed to reduce redundant logic and are mapped into logic blocks and connection lists in the target technology. The operation of the target technology design is simulated using the target logic blocks and connections and the test vectors. The behavioral model is compiled to allow behavioral simulation of the operation of the device using the same test vectors. When the simulation of the target technology and the behavioral model produce identical outputs, the target non-programmable design exactly matches the operation of the prototype programmable device and the target technology design can then be used in mass production of the logic device.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
NORTHROP GRUMMAN CORPORATIONLOS ANGELES, CA1290

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aschliman, Larry D Jacobus, PA 5 136
Kelsey, Randy J Hampstead, MD 5 145

Cited Art

Patent Info (Count) # Cites Year
 
KABUSHIKI KAISHA TOSHIBA (2)
5,067,091 Circuit design conversion apparatus 43 1989
5,276,855 Logic synthesis apparatus for incorporating additional rules to the knowledge base without causing competition 8 1990
 
DATA I/O CORPORATION (1)
4,571,724 System for testing digital logic devices 25 1983
 
FUJITSU LIMITED (1)
5,258,932 PLA simulation method 24 1991
 
HITACHI MICROCOMPUTER ENGINEERING LTD. (1)
4,942,536 Method of automatic circuit translation 56 1986
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,263,149 Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles 36 1991
 
LSI LOGIC CORPORATION (1)
5,339,262 Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC 120 1992
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
5,084,824 Simulation model generation from a physical data base of a combinatorial circuit 136 1990
 
RICOH COMPANY, LTD. (1)
4,922,432 Knowledge based method and apparatus for designing integrated circuits using functional specifications 169 1988
 
TERADYNE, INC. (1)
4,937,770 Simulation system 40 1988
 
U.S. PHILIPS CORPORATION (1)
5,005,136 Silicon-compiler method and arrangement 62 1988
 
VLSI TECHNOLOGY, INC. (1)
4,967,367 Synthetic netlist system and method 82 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
XILINX, INC. (9)
5,734,866 Set of functions for mapping into cell based integrated circuits with fixed number of inputs 1 1995
5,815,405 Method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit 45 1996
5,949,983 Method to back annotate programmable logic device design files based on timing information of a target technology 7 1996
6,219,819 Method for verifying timing in a hard-wired IC device modeled from an FPGA 9 1998
6,018,624 Method to back annotate programmable logic device design files based on timing information of a target technology 10 1999
6,625,788 Method for verifying timing in a hard-wired IC device modeled from an FPGA 12 2000
7,272,542 Method and system for re-targeting integrated circuits 1 2001
7,757,194 Method and system for generating implementation files from a high level specification 0 2007
7,765,508 Method and system for generating multiple implementation views of an IC design 0 2008
 
LSI LOGIC CORPORATION (4)
5,974,248 Intermediate test file conversion and comparison 18 1996
5,995,730 Method for generating format-independent electronic circuit representations 7 1997
6,243,849 Method and apparatus for netlist filtering and cell placement 11 1998
7,096,440 Methods and systems for automatic verification of specification document to hardware design 1 2003
 
VERISITY DESIGN, INC. (4)
6,421,251 Array board interconnect system and method 26 1998
6,134,516 Simulation server system and method 84 1998
6,026,230 Memory simulation system and method 72 1998
6,389,379 Converification system and method 120 1998
 
CADENCE DESIGN SYSTEMS, INC. (3)
5,661,662 Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation 66 1995
5,657,241 Routing methods for use in a logic emulation system 36 1995
5,612,891 Hardware logic emulation system with memory capability 59 1995
 
QUICKTURN DESIGN SYSTEMS, INC. (3)
5,812,414 Method for performing simulation using a hardware logic emulation system 42 1996
5,796,623 Apparatus and method for performing computations with electrically reconfigurable logic devices 33 1996
5,734,581 Method for implementing tri-state nets in a logic emulation system 19 1996
 
RENESAS ELECTRONICS CORPORATION (3)
5,699,283 Logic emulation system 11 1995
6,070,005 Logic emulation system 1 1997
6,282,503 Logic emulation system 7 2000
 
ALTERA CORPORATION (2)
6,321,369 Interface for compiling project variations in electronic design environments 69 1997
7,350,176 Techniques for mapping to a shared lookup table mask 1 2003
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
6,425,109 High level automatic core configuration 42 1999
7,562,320 Asic based conveyor belt style programmable cross-point switch hardware accelerated simulation engine 0 2006
 
NVIDIA CORPORATION (2)
6,502,221 Prototype development system 4 1999
6,618,842 Prototype development system and method 0 2001
 
VERSITY DESIGN, INC. (2)
6,009,256 Simulation/emulation system and method 101 1997
6,321,366 Timing-insensitive glitch-free logic system and method 102 1998
 
AEROFLEX COLORADO SPRINGS INC. (1)
6,453,447 Method for fabricating integrated circuits 26 2000
 
AGILENT TECHNOLOGIES, INC. (1)
6,334,100 Method and apparatus for electronic circuit model correction 7 1998
 
BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY (1)
6,295,535 Method and system for creating designs using internet-based agents 9 1998
 
COMCAST IP HOLDINGS I, LLC (1)
7,155,711 Method and apparatus providing remote reprogramming of programmable logic devices using embedded JTAG physical layer and protocol 4 2000
 
COMPUTER ASSOCIATES THINK, INC. (1)
6,014,697 Method and apparatus for automatically populating a network simulator tool 36 1996
 
ET INTERNATIONAL, INC. (1)
8,365,111 Data driven logic simulation 0 2009
 
FREESCALE SEMICONDUCTOR, INC. (1)
5,666,288 Method and apparatus for designing an integrated circuit 76 1995
 
GENERAL ELECTRIC COMPANY (1)
5,920,830 Methods and apparatus for generating test vectors and validating ASIC designs 22 1997
 
GOOGLE INC. (1)
7,219,046 Characterizing input/output models 0 2003
 
LUCENT TECHNOLOGIES INC. (1)
6,311,146 Circuit simulation with improved circuit partitioning 2 1997
 
MITEL SEMICONDUCTOR LIMITED (1)
6,460,164 Integration of externally developed logic in a memory mapped system 1 1999
 
NEC CORPORATION (1)
5,721,690 Logic circuit synthesis 10 1995
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,790,771 Apparatus and method for configuring a reconfigurable electronic system having defective resources 35 1996
 
SUN MICROSYSTEMS, INC. (1)
6,684,372 Method, system and computer product to translate electronic schematic files between computer aided design platforms 2 2002
 
U.S. ROBOTICS CORPORATION (1)
5,883,809 Behavioral language models for testing and verification of digital electronic circuits 17 1996
 
VLSI TECHNOLOGY, INC. (1)
5,541,850 Method and apparatus for forming an integrated circuit including a memory structure 26 1994
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
5,633,813 Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits 51 1994