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Abstract

A local network system is provided using ATM-like framing and cells for data transmission. A bus architecture is defined, making the cost per port relatively low compared to matrix switching. For high performance, the bus is bit parallel instead of being a serial link. Like other LANs, the average bandwidth per interface (per port) is a low percentage of the peak bandwidth. A single physical bus is used to interconnect a potentially large number of ATM interfaces, on the order of hundreds. The system employs a bus master which provides timing and resolves all arbitration requests. Interfaces connected to the bus are allotted at least one cell per frame for sending data, and write to the allotted cell in synchronization with the frame, cell and bit clocks circulated on the bus from the master. There are more cells than interfaces, so when an interface has a large data block to send it asks for allocation of more cells per frame, and the request is granted by the master coordinated with other demands on the system. This bus arrangement allows construction of a switching system providing asynchronous transfer mode (ATM) cell switching with an aggregate throughput defined by the bus transfer speed, potentially in the multi-gigabit range, while also allowing the bus to be used for pre-arbitrated (isochronous) transmission. The bus uses a 'traveling wave' technique to allow arbitrary physical length (many times the transit distance of one bus cycle) while using a simple, lower-speed sub-bus for bandwidth arbitration.

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