Partially resettable, segmented DMA counter
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United States of America Patent
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Sep 19, 1995
Issued Date -
N/A
app pub date -
Jul 23, 1993
filing date -
Aug 14, 1990
priority date (Note) -
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status (Latency Note)
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Abstract
A direct memory access (DMA) controller (4) utilizes a segmented counter (220). A first, byte counter portion (330) of the counter is initialized with a preselected value and decremented for each byte transfer. After the byte portion of the counter reaches the preselected value it decrements a second, block portion (332) of the counter which is initialized based upon the amount of data to be transferred. When both the byte counter and the block counter reach zero the data transfer is completed.
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