System for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second bus
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United States of America Patent
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Sep 26, 1995
Issued Date -
N/A
app pub date -
Nov 12, 1992
filing date -
Sep 18, 1991
priority date (Note) -
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Abstract
An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.
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