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Abstract

A method of making a DRAM cell capable of increasing storage capacity and for which is amenable to large-scale integration. The method provides a DRAM cell having stacked and trench capacitors and a transistor of second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type. Polycrystalline silicon of a cell node in the stack capacitor is coupled to source region of the transistor. Cell node of the trench capacitor is coupled to the source region of transistor through N-type diffusion region around the trench that is formed between said source region and a field oxide. Over the trench capacitor is disposed the stack capacitor, and the cell nodes are coupled to each other. A cell plate filling the inside of the trench may be used in common since it surrounds the polycrystalline silicon, that is, the cell node of stack capacitor.

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First Claim