Comparator controlled delay-on-break devices
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United States of America Patent
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-
Oct 3, 1995
Grant Date -
N/A
app pub date -
Oct 12, 1993
filing date -
Oct 12, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A delay-on-break circuit adaptable for A.C. or D.C. applications utilizes a timer and a pair of comparators to prevent a load from being re-energized until at least a predetermined period of time has elapsed since the most recent deenergization of the load. A feedback element, such as a zener diode, connected between the output of one of the comparators and a feedback input thereof provides reliable latching of the load through zero crossings of the line in A.C. applications without use of a latching capacitor while simultaneously providing brownout protection capable of rapidly deenergizing the load in the event of an undesired decrease in line voltage.
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