Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
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United States of America Patent
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Oct 3, 1995
Grant Date -
N/A
app pub date -
Dec 6, 1993
filing date -
Dec 6, 1993
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.
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