Importance

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Abstract

A high speed/low overhead bus arbitration apparatus for allocating system bus mastership in a system containing two processing devices. The apparatus includes control logic which controls the access of each of the processing devices to the system bus. The apparatus further includes a multiplexer for selecting the control information presented on the system bus based upon the state of the control logic. The apparatus finally includes a latch for alternatively passing through to and latching onto the system bus, based upon the state of the control logic, an address, which is driven by only one of the processing devices. The control logic transfers access to the system bus from the first processing device to second when the second requests access and the bus is not busy, preventing both processing devices from contending for the system bus by forcing the driving processor device to relinquish the address lines prior to completion of the current bus cycle. The control logic further transfers access to the system bus back to the first processing device when the first requests access and the bus is not busy.

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First Claim