Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA
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United States of America Patent
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-
Oct 10, 1995
Grant Date -
N/A
app pub date -
Nov 23, 1994
filing date -
Nov 23, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A field programmable gate array (FPGA) which verifies that an incoming bitstream is intended for it prior to writing configuration data to programmable memory cells is described. The bitstream has an identification frame which includes an identification code for the targeted FPGA. A verification circuit in a memory controller verifies whether the bitstream is intended for the FPGA based upon the identification code. If the bitstream is intended for the FPGA, the configuration data is processed and stored in the programmable memory cells. If the bitstream is not intended for the FPGA, the FPGA may enter a standby mode, and the configuration process may be halted until a user resets the FPGA. The verification circuit can help prevent damage that may occur to the FPGA when bitstreams intended for a different size memory cell array are received by the FPGA.
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