Apparatus and method for digital circuit testing
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United States of America Patent
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Oct 17, 1995
Grant Date -
N/A
app pub date -
Jan 26, 1994
filing date -
Jan 26, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus and method for digital circuit testing in which latches store a single command for each assigned node in a circuit to be tested. Buffers are used to drive the nodes of the circuit being tested in accordance with the drive commands. The outputs from the circuit being tested are selectively applied to at least one comparator. A multiplexor reduces the number of comparators required for accessing the all pertinent nodes of the digital circuit being tested.
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