Method for fabricating connection device with reduced area of highly integrated semiconductor device
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United States of America Patent
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Oct 24, 1995
Grant Date -
N/A
app pub date -
Dec 27, 1993
filing date -
Dec 30, 1992
priority date (Note) -
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Abstract
A semiconductor connection device capable of reducing the area of connection portions by minimizing an overlapping area between a lower first conduction line and an upper second conduction line at a contact region defined in the first conduction line upon connecting the second conduction line to the first conduction line. The minimized overlapping area can be obtained by forming the second conduction line in a self-aligned manner.
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