Importance

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Abstract

A semiconductor wafer has multiple individual dies containing integrated circuits arrayed for singulation and test cycling circuitry for test cycling individual dies. A passivation layer overlies the dies, with contact openings being provided through the passivation layer to Vcc and Vss pads. The semiconductor wafer also has Vcc and Vss buses provided atop the passivation layer and overlying the individual dies to connect with the underlying Vcc and Vss pads, respectively. In this manner, application of voltage to the Vcc and Vss buses provides simultaneous test cycling of all the underlying dies on the semiconductor wafer. A semiconductor wafer processing fixture for conducting the burn-in test cycling of such a semiconductor wafer is also disclosed. The fixture has a wafer cavity sized to receive and register the semiconductor wafer in a selected orientation and an electrical connector having pins designed to contact the overlying busing structure on the semiconductor wafer. A Vcc voltage is applied to some of the pins, while a Vss voltage is applied to the remaining pins in order to supply power via the bussing to the entire semiconductor wafer.

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First Claim