Programmable multiplexer logic cell
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United States of America Patent
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-
Oct 31, 1995
Grant Date -
N/A
app pub date -
May 19, 1993
filing date -
Jun 2, 1992
priority date (Note) -
Expired
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Abstract
A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors, five inverters and an OR gate to provide a very fast programmable logic cell.
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