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Abstract

A dual port memory has a plurality of memory cell arrays. Plural bit lines for one word are divided into k groups each including m bit lines, and k data busses are commonly provided for all of the memory cell arrays. Bit selecting circuits control data transfer between the data busses and the memory cell arrays. A shift register circuit includes a plurality of partial shift registers which are serially connected with each other and each of which includes serially connected registers corresponding to the data busses. The shift register circuit carries out parallel data transfer between the data busses and each of the partial shift registers, and serial data transfer between one of the partial shift registers and an outside circuit. A dual port memory is provided in which the number of circuit elements and the surface size of memory chips can be reduced while maintaining a high speed of operation.

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First Claim