Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics
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United States of America Patent
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Oct 31, 1995
Issued Date -
N/A
app pub date -
Aug 4, 1993
filing date -
Nov 6, 1989
priority date (Note) -
Expired
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Abstract
A memory control unit and associated method for changing memory access time are used in a microprocessor system in order to make it possible to alter the number of wait states in accordance with memory characteristics. The memory control unit incorporates a register which holds at least 1 bit of data related to the wait states, outputs a response signal to a central processing unit (CPU) at a timing changed in accordance with the data held in the register, and changes the data held in the register by executing a write cycle under control of the CPU. The memory control unit includes a section for holding fixed data representing a fixed delay time based upon an anticipated access time of a memory unit, in addition to the register which holds variable data representing a variable delay time, and an output circuit which adds the fixed data and variable data to produce data representing a total delay time.
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