Weighted summing circuit
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United States of America Patent
Stats
-
Nov 7, 1995
Grant Date -
N/A
app pub date -
Feb 3, 1994
filing date -
Feb 4, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A weighted summing circuit for minimizing bias voltage influence includes capacitive coupling and a closed loop inverter. The weighted summing circuit inputs the output of a capacitive coupling CP.sub.1 to serially connected first and second inverters INV.sub.1 and INV.sub.2, and includes grounded weighted capacitances C.sub.32 and C.sub.11, capacitance C.sub.21 connecting the first and the second inverters INV.sub.1 and INV.sub.2, and a capacitive coupling CP.sub.1 such that the closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are substantially equal. The closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are balanced.
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