System for monitoring abnormal integrated circuit operating conditions and causing selective microprocessor interrupts
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United States of America Patent
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Nov 7, 1995
Issued Date -
N/A
app pub date -
Oct 5, 1994
filing date -
Oct 19, 1990
priority date (Note) -
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status (Latency Note)
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Abstract
The invention relates to integrated circuits and, notably, to circuits for which it is desired to provide security against any fraudulent usage. The circuits concerned are microprocessor circuits having a program memory, a programmable non-volatile memory, at least one input/output port and an RS register memorizing the signals from sensors of abnormal conditions. This register is accessible by the microprocessor. There is provision for means to check the state of the register immediately before any operation for the writing or erasure of the programmable memory, and immediately before any transmission of data towards the exterior of the input/output port, and means to interrupt the working of the microprocessor if the check reveals abnormal conditions.
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