System for forming test patterns for large scale integrated circuits
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United States of America Patent
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Nov 7, 1995
Issued Date -
N/A
app pub date -
Mar 14, 1995
filing date -
Nov 15, 1989
priority date (Note) -
Expired
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Abstract
A system for forming test patterns of an LSI as a test pattern formation target includes an extraction condition setting means and a state value data acquiring means. The extraction condition setting means sets a state value extraction condition for the LSI. The state value data acquires data of the state values of the input/output pins of the LSI during the logic simulation of a logic circuit including the LSI while the condition set by the extraction condition setting means is satisfied. The test patterns of the LSI are formed on the basis of the data acquired by the state value data acquiring means.
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