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Abstract

An MOS reference voltage generating circuit is provided which has a simplified circuit that eliminates the need for a feedback circuit and a large compensating capacitor, and reduces the current consumption of the device. This is achieved by utilizing a new circuit configuration which is simplified. The simplifier reference potential generating circuit comprises a first PMOS transistor having its gate and its drain connected in common to a first node and its source connected to Vcc, a second PMOS transistor having its gate and its drain connected in common to a second node and its source connected to Vcc, a resistor connected between the first node and the second node, and a first current source connected between the first node and ground. A third PMOS transistor is connected at its gate to the second node and at its source connected to Vcc, so that a current mirror is constituted of the second and third transistors. A fourth PMOS transistor is connected at its source connected to a drain of the third PMOS transistor. A gate of the fourth PMOS transistor is connected to the first node, and a drain of the fourth PMOS transistor is connected to one end of a second resistor having its other end grounded. A reference potential is generated from the one end of the second resistor and is independent of variations in the supply voltage and temperature. This simplified circuit is compatible with standard CMOS processing allowing for low cost manufacturing while obtaining improved operation and reduced circuit area.

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First Claim